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general description the MAX5051 is a clamped, two-switch power-supply controller ic. this device can be used both in forward or flyback configurations with input voltage ranges from 11v to 76v. it provides comprehensive protection mech- anisms against possible faults, resulting in very high relia- bility power supplies. when used in conjunction with sec- ondary-side synchronous rectification, power-supply efficiencies can easily reach 92% for a +3.3v output power supply operated from a 48v bus. the integrated high- and low-side gate drivers provide more than 2a of peak gate-drive current to two external n-channel mosfets. low startup current reduces the power loss across the bootstrap resistor. a feed-forward voltage- mode topology provides excellent line rejection while avoiding the pitfalls of traditional current-mode control. the MAX5051 power-supply controller is primary as well as secondary-side parallelable, allowing the design of scaleable power systems when necessary. when paralleling the primary side, dedicated pins allow for simultaneous wakeup or shutdown of all paralleled units, thus preventing current-hogging during startup or fault conditions. the MAX5051 generates a lookahead signal for driving secondary-side synchronous mosfets. special primary-side synchronization inputs/outputs allow two primaries to be operated 180 out of phase for increased output power and lower input ripple currents. the MAX5051 is available in a 28-pin tssop-ep package and operates over a wide -40? to +125? temperature range. warning: the MAX5051 is designed to work with high voltages. exercise caution. applications high-efficiency, isolated telecom/datacom power supplies 48v and 12v server power supplies 48v power-supply modules 42v automotive power systems industrial power supplies features wide input voltage range, 11v to 76v voltage mode with input voltage feed-forward ripple-phased parallel topology for high current/power output 2a integrated high- and low-side mosfet drivers syncin and syncout pins enable 180 out-of- phase operation programmable brownout and bootstrap uvlos high-side driver bootstrap capacitor precharge driver low current-limit threshold for high efficiency programmable switching frequency reference voltage soft-start for startup without overshoots startup synchronization with multiple paralleled primaries programmable integrating current-limit fault protection look-ahead pwm signal for secondary-side synchronous rectifier drivers look-ahead drivers for either a high-speed optocoupler or pulse transformer wide -40? to +125? operating range thermally enhanced 28-pin tssop package MAX5051 parallelable, clamped two-switch power-supply controller ic ________________________________________________________________ maxim integrated products 1 ordering information 19-2964; rev 0; 8/03 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin-package MAX5051aui -40 c to +125 c 28-tssop-ep* * ep = exposed pad. pin configuration appears at end of data sheet.
MAX5051 parallelable, clamped two-switch power-supply controller ic 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (avin = 12v, pvin = 12v, v uvlo = v stt = 3v, v con = 3v, r rcosc = 24k ? , c css = 10nf, c rcosc = 100pf, c reg9 = 4.7f, c reg5 = 4.7f, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c. all driver, voltage-regulator, and refer- ence outputs unconnected except for bypass capacitors.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. avin, pvin, xfrmrh to gnd................................-0.3v to +80v bst to gnd ............................................................-0.3v to +95v bst, drvh to xfrmrh..........................................-0.3v to +12v reg9, drvdd, drvl to gnd................................-0.3v to +12v drvb, lxvdd, lxl, lxh to gnd ..........................-0.3v to +12v uvlo, stt, comp, con to gnd ..........................-0.3v to +12v fltint, rcff to gnd ............................................-0.3v to +12v reg5, cs, css, fb to gnd .....................................-0.3v to +6v startup, syncin to gnd......................................-0.3v to +6v syncout, rcosc to gnd .....................................-0.3v to +6v pgnd to gnd .......................................................-0.3v to +0.3v lxl, lxh current continuous...........................................50ma drvl, drvh current continuous...................................100ma drvl, drvh peak current (<500ns) ....................................5a pvin, reg9 continuous current ....................................+120ma reg5 continuous current ................................................+80ma drvb, rcff, rcosc, css continuous current .............20ma comp, syncout continuous current ............................20ma reg9, reg5, and comp short to gnd ....................continuous continuous power dissipation (t a = +70 c) 28-pin tssop (derate 23.8mw/ c above +70 c) .....1905mw 28-pin tssop ( ja )......................................................42 c/w operating temperature range .........................-40 c to +125 c maximum junction temperature (t j ) ..............................+150 c storage temperature range .............................-65 c to +150 c lead temperature (soldering, 10s) .................................+300 c parameter symbol conditions min typ max units supply current (avin, pvin) avin standby current i astby 300 450 a pvin standby current i pstby v avin = v pvin = 11v to 76v; v startup = v cs = 0v; v bst = v xfrmrh = v drvdd = v reg9 ; rcff floating 400 650 a avin supply current i avin 0.65 1 ma pvin supply current i pvin v avin = v pvin = 11v to 76v; v cs = 0v; v bst = v drvdd = v reg9 ; v xfrmrh = 0v; startup, rcff floating 812ma avin input voltage range inferred from avin supply current test 11 76 v +9v ldo (reg9) pvin input voltage range v pvin inferred from pvin supply current test 11 76 v reg9 output-voltage set point v reg9 v pvin = 11v 8.3 9.0 v reg9 line regulation v pvin = 11v to 76v 0.1 mv/v reg9 load regulation i reg9 = 0 to 80ma 250 mv reg9 dropout voltage i reg9 = 80ma 0.5 v reg9 undervoltage lockout threshold v reg9 falling 5.7 6.7 v reg9 undervoltage lockout threshold hysteresis 750 mv +5v ldo (reg5) reg5 output-voltage set point v reg5 4.8 5.1 v reg5 load regulation i reg5 = 0 to 40ma 50 mv reg5 dropout voltage i reg5 = 40ma, measured with respect to v reg9 0.5 v
MAX5051 parallelable, clamped two-switch power-supply controller ic _______________________________________________________________________________________ 3 electrical characteristics (continued) (avin = 12v, pvin = 12v, v uvlo = v stt = 3v, v con = 3v, r rcosc = 24k ? , c css = 10nf, c rcosc = 100pf, c reg9 = 4.7f, c reg5 = 4.7f, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c. all driver, voltage-regulator, and refer- ence outputs unconnected except for bypass capacitors.) parameter symbol conditions min typ max units soft-start/reference (css) reference voltage v css 1.215 1.235 1.255 v soft-start pullup current i css 70 a error amplifier (css, fb, comp) fb input range v fb inferred from fb offset voltage test 0 3 v fb input current i fb v fb = v ref 250 na comp output range inferred from fb offset voltage test 2.1 6.0 v comp output sink current v fb = 3v 20 ma comp output source current v fb = 0v 30 ma open-loop gain g a 2.1v < v comp < 6v 80 db unity-gain bandwidth bw c comp = 50pf, i comp = 5ma 3 mhz fb offset voltage v os v fb = 0 to 3v; v comp = 2.1v to 6v; i comp = -5ma to +5ma -3 +3 mv comp output slew rate sr c comp = 50pf 1 v/s pvin undervoltage lockout (stt) pvin undervoltage lockout v pvin rising 22 23.5 25 v stt threshold v stt v stt rising 1.18 1.24 1.30 v stt input impedance r stt 100 k ? integrating fault protection (fltint) fltint source current i fltint v fltint = 0v 90 a fltint shutdown threshold v fltintsd v fltint = rising 2.9 v fltint restart hysteresis v fltinthy 0.9 v oscillator (rcosc, syncin, syncout) pwm period t s r rcosc = 24k ? , c rcosc = 100pf 3.9 s maximum pwm duty cycle d max r rcosc = 24k ? , c rcosc = 100pf 48 % maximum rcosc frequency f rcoscmax 1 mhz maximum syncin frequency f syncin 50% duty cycle 500 khz syncin high-level voltage vh syncin pulse rising 2.1 v syncin low-level voltage vl syncin pulse falling 0.8 v syncin pulldown resistor 100 k ? syncin rising to syncout falling delay 30 ns syncin falling to syncout rising delay 70 ns
MAX5051 parallelable, clamped two-switch power-supply controller ic 4 _______________________________________________________________________________________ electrical characteristics (continued) (avin = 12v, pvin = 12v, v uvlo = v stt = 3v, v con = 3v, r rcosc = 24k ? , c css = 10nf, c rcosc = 100pf, c reg9 = 4.7f, c reg5 = 4.7f, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c. all driver, voltage-regulator, and refer- ence outputs unconnected except for bypass capacitors.) parameter symbol conditions min typ max units syncout voltage high sourcing 1.2ma 4.5 5.1 v syncout voltage low sinking 2.4ma 0.3 v rcosc peak trip level v th 2.5 v rcosc valley trip level 0.2 v rcosc input bias current -0.3 a rcosc discharge mosfet r ds(on) sinking 10ma 50 100 ? rcosc discharge pulse width 50 ns undervoltage lockout (uvlo) uvlo threshold v uvlo v uvlo rising 1.18 1.24 1.30 v uvlo hysteresis v hys 130 mv uvlo input bias current i buvlo v uvlo = 2.5v -100 +100 na pwm comparator rcff input voltage range 0 3 v feed-forward discharge mosfet r ds(on) r ds ( rcff ) sinking 10ma 50 100 ? con input voltage range 06v rcff level-shift voltage v cpwm 2.2 2.4 v con input bias current i con -2 +2 a propagation delay to output t dcpwm drvh, drvl = unconnected, overdrive = 50mv, measured from con to drvl 90 ns synchronous rectifier pulse transformer driver (lxvdd, lxh, lxl) high-side mosfet r ds(on) r dslxh lxh sourcing 10ma, v lxvdd = v reg5 3 6.5 12 ? low-side mosfet r ds(on) r dslxl lxl sinking 10ma, v lxvdd = v reg5 2.0 5 10 ? lxh rising to drvl rising delay 90 ns current-limit comparator (cs) current-limit threshold voltage v ilim 144 154 164 mv current-limit input bias current i bilim 0 < v cs < 0.3v -2 +2 a propagation delay to output t dilim drvh, drvl = unconnected, overdrive = 10mv, measured from cs to drvl 100 ns low-side mosfet driver (drvdd, drvl, pgnd) peak source current v drvl = 0v, pulse width < 100ns; v drvdd = v reg9 2a peak sink current v drvl = v reg9 , pulse width < 100ns; v drvdd = v reg9 5a drvl resistance sourcing i drvl = 50ma, v drvdd = v reg9 1.7 3.5 ? drvl resistance sinking i drvl = -50ma, v drvdd = v reg9 0.6 1.4 ?
MAX5051 parallelable, clamped two-switch power-supply controller ic _______________________________________________________________________________________ 5 electrical characteristics (continued) (avin = 12v, pvin = 12v, v uvlo = v stt = 3v, v con = 3v, r rcosc = 24k ? , c css = 10nf, c rcosc = 100pf, c reg9 = 4.7f, c reg5 = 4.7f, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c. all driver, voltage-regulator, and refer- ence outputs unconnected except for bypass capacitors.) parameter symbol conditions min typ max units high-side mosfet driver (bst, drvh, xfrmrh) peak source current v d rv h = gn d , p ul se w i d th < 100ns, v b s t = v r e g9 , v x fr m r h = 0v 2a peak sink current v d rv h = v b s t , p ul se w i d th < 100ns, v b s t = v r e g9 , v x fr m r h = 0v 5a drvh resistance sourcing i drvh = 50ma, v bst = v reg9 , v xfrmrh = 0v 1.7 3.5 ? drvh resistance sinking i drvh = -50ma, v bst = v reg9 , v xfrmrh = 0v 0.6 1.4 ? skew between low-side and high-side drivers 0ns boost capacitor charge mosfet (drvb) drvb resistance sourcing i drvb = 50ma 8 35 ? drvb resistance sinking i drvb = 50ma 5 35 ? delay from clock fall 200 ns one-shot pulse width 300 ns startup (startup) startup threshold v startup v startup rising 1.4 2.1 v startup threshold hysteresis 330 mv internal pullup current i startup 50 a s tartu p p ul l d ow n m os fe t r d s ( on ) sinking 10ma 50 100 ? overtemperature shutdown shutdown junction temperature temperature rising 150 c hysteresis 10 c
MAX5051 parallelable, clamped two-switch power-supply controller ic 6 _______________________________________________________________________________________ typical operating characteristics (v avin = v pvin = 12v, v uvlo = v stt = 3v, v con = 3v, r rcosc = 24k ? , c css = 10nf, c rcosc = 100pf, c reg9 = 4.7f, c reg5 = 4.7f, t a = +25 c, unless otherwise noted.) avin standby current vs. avin supply voltage MAX5051 toc01 avin supply voltage (v) avin standby current ( a) 70 60 40 50 30 20 210 220 230 240 250 260 270 280 290 300 200 10 80 v uvlo = 0v avin standby current vs. temperature MAX5051 toc02 temperature ( c) avin standby current ( a) 100 75 25 50 0 -25 210 220 230 240 250 260 270 280 200 190 180 -50 125 v uvlo = 0v pvin standby current vs. supply voltage MAX5051 toc03 pvin supply voltage (v) pvin standby current ( a) 70 60 50 40 30 20 100 200 300 400 500 600 0 10 80 v uvlo = 0v pvin standby current vs. temperature MAX5051 toc04 temperature ( c) pvin standby current ( a) 100 75 50 25 0 -25 100 200 300 400 500 600 0 -50 125 v uvlo = 0v pvin startup voltage vs. temperature MAX5051 toc05 temperature ( c) pvin startup voltage (v) 100 75 50 25 0 -25 23.1 23.2 23.3 23.4 23.5 23.6 23.0 -50 125 stt = floating reg9 output voltage vs. pvin voltage MAX5051 toc06 pvin voltage (v) reg9 output voltage (v) 70 60 50 40 30 20 8.793 8.796 8.799 8.802 8.805 8.970 10 80 reg9 output voltage vs. temperature MAX5051 toc07 temperature ( c) reg9 output voltage (v) 100 75 25 50 0 -25 8.72 8.74 8.76 8.78 8.80 8.82 8.84 8.86 8.88 8.90 8.70 -50 125 reg9 output voltage vs. reg9 output current MAX5051 toc08 reg9 output current (ma) reg9 output voltage (v) 140 120 80 100 40 60 20 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 9.0 8.0 0 160 reg5 output voltage vs. reg5 output current MAX5051 toc09 reg5 output current (ma) reg5 output voltage (v) 80 70 60 50 40 30 20 10 4.4 4.8 5.2 5.6 6.0 4.0 090
MAX5051 parallelable, clamped two-switch power-supply controller ic _______________________________________________________________________________________ 7 reg5 output voltage vs. temperature MAX5051 toc10 temperature ( c) output voltage (v) 100 75 25 50 0 -25 4.991 4.992 4.993 4.994 4.995 4.996 4.997 4.998 4.999 5.000 5.001 4.990 -50 125 avin supply current vs. temperature MAX5051 toc11 temperature ( c) avin supply current ( a) 100 75 50 25 0 -25 100 200 300 400 500 600 700 0 -50 125 v uvlo = 0v pvin supply current vs. temperature MAX5051 toc12 temperature ( c) pvin supply current (ma) 100 75 50 25 0 -25 6.7 6.8 6.9 7.0 7.1 7.2 6.6 -50 125 v pvin = 12v soft-start/reference voltage vs. temperature MAX5051 toc13 temperature ( c) soft-start/reference voltage (v) 100 75 25 50 0 -25 1.200 1.205 1.210 1.215 1.220 1.225 1.230 1.235 1.240 1.245 -50 125 css soft-start current vs. temperature MAX5051 toc14 temperature ( c) css soft-start current ( a) 100 75 50 25 0 -25 65 70 75 80 85 90 60 -50 125 uvlo threshold vs. temperature MAX5051 toc15 temperature ( c) uvlo (v) 100 75 -25 0 25 50 1.205 1.210 1.215 1.220 1.225 1.230 1.235 1.240 1.200 -50 125 stt startup threshold vs. temperature MAX5051 toc16 temperature ( c) stt (v) 100 75 -25 0 25 50 1.205 1.210 1.215 1.220 1.225 1.230 1.235 1.240 1.200 -50 125 fltint current vs. temperature MAX5051 toc17 temperature ( c) fltint current ( a) 100 75 25 50 0 -25 86 85 87 88 89 90 91 92 93 94 95 -50 125 rcff level-shift voltage vs. temperature MAX5051 toc18 temperature ( c) rcff level-shift voltage (v) 100 75 25 50 0 -25 2.21 2.22 2.23 2.24 2.25 2.26 2.27 2.28 2.29 2.30 2.20 -50 125 typical operating characteristics (continued) (v avin = v pvin = 12v, v uvlo = v stt = 3v, v con = 3v, r rcosc = 24k ? , c css = 10nf, c rcosc = 100pf, c reg9 = 4.7f, c reg5 = 4.7f, t a = +25 c, unless otherwise noted.)
MAX5051 parallelable, clamped two-switch power-supply controller ic 8 _______________________________________________________________________________________ current-limit threshold vs. temperature MAX5051 toc19 temperature ( c) cs threshold voltage (mv) 100 75 50 25 0 -25 145 150 155 160 165 170 140 -50 125 -20 0 20 40 60 80 100 270 240 210 180 150 120 90 60 30 0 open-loop gain/phase vs. frequency frequency (khz) 0.01 10 100 1000 0.1 1 10,000 gain (db) phase (degrees) MAX5051 toc20 gain phase comp output voltage vs. temperature MAX5051 toc21 temperature ( c) comp output voltage (v) 100 75 -25 0 25 50 1 2 3 4 5 6 7 8 0 -50 125 i source = 5ma i sink = 5ma drvh and drvl r dson vs. temperature MAX5051 toc22 temperature ( c) r dson ( ? ) 100 75 -25 0 25 50 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 -50 125 drvh and drvl sourcing 50ma drvh and drvl sinking 50ma lxl and lxh r dson vs. temperature MAX5051 toc23 temperature ( c) r dson ( ? ) 85 60 -15 10 35 5 6 7 8 9 10 11 12 4 -40 110 lxh sourcing 10ma lxh sinking 10ma switching period vs. r rcosc MAX5051 toc24 r rcosc (k ? ) switching period ( s) 160 120 80 40 5 10 15 20 25 30 35 40 45 50 0 0200 normalized switching frequency vs. temperature MAX5051 toc25 temperature ( c) normalized switching frequency 100 75 50 25 0 -25 0.960 0.970 0.980 0.990 1.000 1.010 1.020 0.950 -50 125 switching syncin to syncout propagation delay vs. temperature MAX5051 toc26 temperature ( c) propagation delay (ns) 100 75 25 50 0 -25 40 50 60 70 80 90 100 110 120 130 30 -50 125 syncin fall to syncout rise syncin rise to syncout fall drvh maximum duty cycle vs. temperature MAX5051 toc27 temperature ( c) drvh duty cycle (%) 100 75 25 50 0 -25 46.4 46.8 47.2 47.6 48.0 48.4 48.8 49.2 49.6 50.0 46.0 -50 125 typical operating characteristics (continued) (v avin = v pvin = 12v, v uvlo = v stt = 3v, v con = 3v, r rcosc = 24k ? , c css = 10nf, c rcosc = 100pf, c reg9 = 4.7f, c reg5 = 4.7f, t a = +25 c, unless otherwise noted.)
MAX5051 parallelable, clamped two-switch power-supply controller ic _______________________________________________________________________________________ 9 pin description con to drvl propagation delay vs. temperature MAX5051 toc28 temperature ( c) propagation delay (ns) 100 75 25 50 0 -25 65 70 75 80 85 90 95 100 105 110 60 -50 125 50mv overdrive cs current limit to drvh propagation delay vs. temperature MAX5051 toc29 temperature ( c) propagation delay (ns) 100 75 50 25 0 -25 90 100 110 120 130 140 150 80 -50 125 50mv overdrive typical operating characteristics (continued) (v avin = v pvin = 12v, v uvlo = v stt = 3v, v con = 3v, r rcosc = 24k ? , c css = 10nf, c rcosc = 100pf, c reg9 = 4.7f, c reg5 = 4.7f, t a = +25 c, unless otherwise noted.) pin name function 1 rcosc osci l l ator fr eq uency s et inp ut. c onnect a r esi stor fr om rc os c to re g5 and a cap aci tor fr om rc os c to gn d to set the osci l l ator fr eq uency. s w i tchi ng fr eq uency i s 1/2 the fr eq uency of the saw tooth si g nal at rc os c . 2 syncout synchronization output. synchronization signal to drive syncin of a second MAX5051, if used. 3 rcff feed-forward input. connect a resistor from rcff to avin and a capacitor from rcff to gnd. this is the pwm ramp. 4 con pwm comparator noninverting input. connect con to the optocoupler output for isolated applications, or to comp for nonisolated applications. 5 css soft-start and reference. connect a 0.01f or greater capacitor from css to gnd. the 1.24v reference voltage appears across this capacitor. 6 comp internal error amplifier output 7fb feedback input. inverting input of the internal error amplifier. the soft-started reference is connected to the noninverting input of this amplifier. 8 reg5 5v linear regulator output. bypass reg5 to gnd with a 4.7f ceramic capacitor. 9 reg9 9v linear regulator output. bypass reg9 to gnd with a 4.7f ceramic capacitor. 10 pvin regulator voltage input. voltage input to the internal 5v and 9v linear regulators. a high-value resistor connected from the input supply to pvin provides the necessary current to charge up the startup capacitor, and the 400a standby current required by the MAX5051. after startup, the output of a tertiary winding is used to provide continued bias to the controller. 11 stt startup threshold input. leave stt floating for a default startup voltage of 24v at pvin. stt can be modified by connecting external resistors. for high accuracy, choose external resistors with 50k ? or less impedance looking back into the divider. 12 lxvdd supply input for the secondary-side synchronous pulse transformer or optocoupler driver. lxvdd is normally connected to reg5.
MAX5051 parallelable, clamped two-switch power-supply controller ic 10 ______________________________________________________________________________________ pin description (continued) pin name function 13 lxh synchronous-pulse transformer driver, pmos open drain. lxh is the high-side driver for the secondary- side synchronous-pulse transformer. lxh can also drive a high-speed switching optocoupler. if not used, connect lxh to lxvdd. 14 lxl synchronous-pulse transformer driver, nmos open drain. lxl is the low-side driver for the secondary- side synchronous-pulse transformer. lxl can also drive a high-speed switching optocoupler. if not used, connect lxl to pgnd. 15 cs current-sense input. the current-limit threshold is internally set to 156mv relative to pgnd. the device has an internal noise filter. if necessary, connect an additional external rc filter. 16 drvl gate-drive output for low-side mosfet. drvl is capable of sourcing and sinking approximately 2a peak current. 17 pgnd power ground 18 drvdd supply input for low-side mosfet driver. bypass drvdd locally with good quality 1f || 0.1f ceramic capacitors. drvdd is normally connected to reg9. 19 drvb gate-drive output for boost mosfet. connect the gate of a small high-voltage external fet to this pin to enable charging of the high-side boost capacitor connected between pins 20 and 22. this fet may be necessary to keep the boost capacitor charged at light loads. 20 xfrmrh transformer input. transformer primary high-side connection. 21 drvh gate-drive output for high-side mosfet 22 bst boost input. boost supply connection point for the high-side mosfet driver. connect at least a 1f || 0.1f ceramic capacitor from bst to xfrmrh with short and wide pc board traces. if the voltage across the boost capacitor falls below the high-side undervoltage lockout threshold, the drvh output stops switching. 23 avin supply voltage input. connect avin directly to the input supply line. 24 gnd analog signal ground 25 uvlo undervoltage lockout input. an external voltage-divider from the input supply sets the startup voltage; the threshold is 1.24v with 130mv hysteresis. uvlo can also be used as a shutdown input. if unused, connect uvlo to reg5 26 startup startup input. startup coordinates simultaneous startup of multiple units from faults, during initial turn- on, and uvlo recovery. when paralleling the secondaries of two MAX5051 s, the startup inputs of each device must be connected together. 27 fltint faul t integ r ati on inp ut. d ur i ng p er si stent cur r ent- l i m i t faul ts, a cap aci tor connected to fltin t i s char g ed w i th an i nter nal 90a cur r ent sour ce. s w i tchi ng i s ter m i nated w hen the vol tag e r eaches 2.9v . an exter nal r esi stor connected i n p ar al l el d i schar g es the cap aci tor . s w i tchi ng r esum es w hen the vol tag e d r op s to 2v . 28 syncin synchronization input. syncin accepts the synchronization signal from syncout of another MAX5051 and shifts the switching of the synchronized unit by 180 allowing the reduction of input bypass capacitors. the MAX5051 switches at the same frequency at syncin. syncin must be 50% duty cycle. leave syncin floating if unused.
MAX5051 parallelable, clamped two-switch power-supply controller ic ______________________________________________________________________________________ 11 MAX5051 cpwm e/a 1 ssa 9v ldo 5v ldo reg5 ok 80 a reg9 reg5 bst drvh xfrmrh drvl pgnd lxvdd lxh lxl fltint cs avin uvlo stt osc rcosc rcff fb comp css cilim syncin syncout startup 50 a gnd 64 a r 18r 1.25v 1.125v 1.25v 1.125v drvdd pvin reg9 ok con 1.25v over temp shdn 2.34v 156mv 10mhz d s r q internal regulator internal supply 1.25v reference thermal shutdown 2.7v/1.8v 2.7v/1.8v drvb 200ns rising- edge delay drvdd shdn q 300ns one shot level shift level shift level shift 60ns rising- edge delay 25 s rising- edge delay shdn functional diagram
MAX5051 detailed description the MAX5051 controller ic is designed for two-switch forward converter power-supply topologies. it incorpo- rates an advanced set of protection features that makes it uniquely suitable when high reliability and comprehensive fault protection are required, as in power supplies intended for telecommunication equipment. the device operates over a wide 11v to 76v supply range. by using the MAX5051 with a secondary-side synchronous rectifier circuit, a very efficient low output voltage and high output-current power supply can be designed. in a typical application, the avin pin is connected directly to the input supply. the pvin pin is connected to the input supply through a bleed resistor. this is used to charge up a reservoir capacitor. when the voltage across this capacitor reaches approximately 24v, then primary switching commences. if the tertiary winding is able to supply bias to the ic, then self boot-strapping takes place and operation continues normally. if the voltage across the reservoir capacitor connected to pvin falls below 6.2v, then switching stops and the capacitor starts charging up again until the voltage across it reaches 24v. this device incorporates synchronization circuitry, enabling the direct paralleling of two devices for higher output power and lower input ripple current. using a single pin, the circuitry synchronizes and shifts the phase of the second device by 180 . to enable simul- taneous wakeup and shutdown, a startup pin is pro- vided. connect all the startup pins of all MAX5051 devices together to facilitate parallel operation in the primary side. when each power supply generates dif- ferent output voltages, connecting the startup pins is not necessary. power topology the two-switch forward-converter topology offers outstanding robustness against faults and transformer saturation while allowing the use of so-8 power mosfets with a voltage rating equal to only that of the input supply voltage. voltage-mode control with feed-forward compensation allows the rejection of input supply disturbances within a single cycle, similar to that of current-mode controlled topologies. this control method offers some significant benefits not possible with current-mode control. these benefits are: no minimum duty-cycle requirement because of cur- rent-signal blanking; clean modulator ramp and higher amplitude for increased stability; stable operating current of the optocoupler led and phototransistor for maximized control-loop band- width (in current-mode applications, the optocoupler bias point is output-load dependent); predictable loop dynamics simplifying the design of the control loop. the two-switch power topology has the added benefit of recovering practically all magnetizing as well as the leakage energy stored in the parasitics of the isolation transformer. the lower clamped voltages on the prima- ry power fets allow for the use of low r ds(on) devices. figure 2 shows the schematic diagram of a 48v input 3.3v/10a output power supply built around the MAX5051. mosfet drivers the MAX5051 s integrated high- and low-side mosfet drivers source and sink up to 2a of peak currents, resulting in very low losses even when switching high gate charge mosfets. the high-side gate driver requires its own bypass capacitor connected between bst and xfrmrh. use high-quality ceramic capacitors close to these two pins for bypass. under normal oper- ating conditions, the energy stored in the transformer parasitics swings the xfrmrh pin to ground while the transformer is resetting. during this time, the charge on the boost capacitor connected to the bst pin is replen- ished. however, under certain conditions, such as when the magnetizing inductance of the transformer is very high or when using conventional rectification at the output, the duty cycle with light loads may become very small. thus, the energy stored could be insufficient to swing xfrmrh to ground and replenish the boost capacitor. figure 3 shows the equivalent circuit during the magnetizing inductance reset interval, assuming synchronous rectification where the output inductor is not allowed to run discontinuous. if the magnetizing inductance is kept below the follow- ing minimum, then the boost capacitor charge will not deplete: where d is the duty cycle, v in is the input voltage, f s is the switching frequency, and q gtotal is the total gate charge for the high-side mosfet. the above formula is only an approximation; the actual value will depend on other parasitics as well. ld v fqg af m in s total s + 0 294 0 005 2 2 . (. ) parallelable, clamped two-switch power-supply controller ic 12 ______________________________________________________________________________________
if the charge stored on the boost capacitor is not ade- quately replenished then the gate-driver lockout for the high-side mosfet is triggered, stopping the high side from switching. the low side continues switching, even- tually recharging the capacitor, at which point the high side starts switching again. to prevent this behavior, use the boost capacitor s cycle-by-cycle charging cir- cuit to prevent unwanted shutdowns of the high side (figure 2). connect the gate of a small high-voltage fet (with the same voltage rating or higher as the main fets) to the drvb output of the MAX5051. connect the drain of this fet to xfrmrh, and connect the source to the primary ground. drvb will briefly (300ns) turn this fet on every cycle after the main pwm clock ter- minates. this allows the boost capacitor to be replen- ished under all conditions, even when switching stops completely. a suitable fet for this is bss123 or equiva- lent (100v, 170ma rated). the boost-capacitor charge MAX5051 parallelable, clamped two-switch power-supply controller ic ______________________________________________________________________________________ 13 MAX5051 t1 u2 con fltint gnd rcff rcosc startup fb bst reg9 syncin pvin avin css stt drvb xfrmrh drvh drvdd drvl pgnd cs comp uvlo reg5 syncout lxvdd lxh lxl v in+ 3.3v 10a b2100 t1 l m : 150 h p: 14t s: 4t t: 6t r load max8515 used for boost capacitor precharge ps2913 v in- fs = 250khz r12 1m ? c12 220nf c13 100pf c14 390pf r13 100k ? r14 24.9k ? r15 1m ? r11 39.2k ? c10 4.7 f c9 1 f r10 10 ? r8 2.2k ? r7 360 ? c6 270nf r1 11.5k ? r2 2.55k ? c1 47nf c2 220nf r3 475 ? c3 150nf c4 3 x 270 f l1 2 h d5 d2 b2100 d1 n1 si4486 n2 si4486 n3 bss123 r4 28m ? c5 1 f c7 4.7 f r5 10 ? d3 bat46w r6 47 ? c8 4.7 f d4 ma111ct r9 15k ? c11 0.1 f figure 2. typical application circuit v in reg9 i bst i bst l m i gd i lm drvl drvh xfmrh bst figure 3. boost capacitor charging path during transformer reset
MAX5051 diode is a high-voltage, small-signal schottky type. it may be helpful to connect a resistor in series with this diode to minimize noise as well as reduce the peak charging currents. as in any other switching power- supply circuit, the gate-drive loops must be kept to a minimum. plan pc board layout with the critical current carrying loops of the circuit as a starting point. secondary-side synchronization the MAX5051 has additional (lxh and lxl) outputs to make the driving of secondary-side synchronous recti- fiers possible with a signal from the primary. these sig- nals lead in time, the actual gate drive applied to the main power fets, and allow the secondary-side syn- chronous fets to be commutated in advance of the power pulse. the synchronizing pulse is generated approximately 90ns ahead of the main pulse that drives the two power fets. synchronization is accomplished by connecting a small pulse transformer between lxh and lxl, along with some clamp diodes (d1 and d2 in figure 4). this is a small integrated two-switch driver configuration that allows for full recovery of the stored energy in the mag- netizing inductance of the pulse transformer, thereby significantly reducing the running bias current of the controller. it also allows for correct transfer of dc levels without requiring series capacitors with large time con- stants, assuring correct drive levels for the secondary circuit. select a pulse transformer, t1, so the current buildup in its magnetizing inductance is low enough not to create a significant voltage droop across the internal driver fets. use the following formula to calculate the approximate value of the primary magnetizing induc- tance of t1: where r dslxh and r dslxl are the internal high- and low- side pulse transformer driver on-resistances, f s is the switching frequency, l m is the pulse transformer primary magnetizing inductance, t s is the transition time at the drains of these fets (typically < 40ns), and c ds is the total drain-source capacitance (approximately 10pf). alternatively, a high-speed optocoupler (figure 5) can be used instead of the pulse transformer. the look- ahead pulse accommodates the propagation delays of the high-speed optocoupler as well as the delays through the gate drivers of the secondary-side fets. choose optocouplers with propagation delays of less than 50ns. error amplifier and reference soft-start the error amplifier in the MAX5051 has an uncommitted inverting input (fb) and output (comp). use this ampli- fier when secondary isolation is not required. comp can then be directly connected to con (the input of the pwm comparator). the noninverting input of the error amplifier is connected to the soft-start generator and is also available externally at css. a capacitor connected to css is slewed linearly during initial startup with the 70a internal current source (see figure 2). this pro- vides a linearly increasing reference to the noninverting input of the error amplifier forcing the output voltage also to slew proportionally. this method of soft-start is superior to other methods because the loop is always 25 16 . rr f l t cf dslxh dslxl s m s ds s + ? parallelable, clamped two-switch power-supply controller ic 14 ______________________________________________________________________________________ MAX5051 t1 lxh reg5 lxvdd lxl pgnd r1 4.7 ? c1 1 f d1 d2 d3 1n4148 r2 2k ? t1: pulse engineering, pe-68386. d1, d2: central semiconductor, cmosh-3. figure 4. secondary-side synchronous rectifier driver using pulse transformer MAX5051 lxh reg5 lxvdd lxl pgnd c1 1 f r1 4.7 ? r2 2k ? r3 560 ? ps9715 high-speed opto 5v c2 u2 figure 5. secondary-side synchronous rectifier driver using high-speed optocoupler
in control. thus, the output-voltage slew rate is constant at light or heavy loads. once the soft-start ends, the voltage on css regulates to 1.24v. do not load css with external circuitry. a suitable range of capacitors connected to css is from 10nf to 0.1f. calculate the required soft-start capacitor based on the total output- voltage startup time as follows: where c css is the capacitor connected to css, t ss is the soft-start time required for the output voltage to rise from 0v to the rated output voltage. this only applies when this amplifier is used for output voltage regulation. pwm ramp the pwm ramp is generated at rcff. connect a capacitor c rcff from rcff to ground and a resistor r rcff from rcff to avin. the ramp generated on rcff is internally offset by 2.3v and applied to the non- inverting input of the pwm comparator. the slope of the ramp is part of the overall loop gain. the dynamic range of rcff is 0 to 3v, and so the ramp peak must be kept below that. assuming the maximum duty cycle approaches 50% at minimum input voltage, use the fol- lowing formula to calculate the minimum value of either the ramp capacitor or resistor: where v inuvlo is the minimum input supply voltage (typically the pwm uvlo turn-on voltage), f s is the switching frequency, and v rpp is the peak-to-peak ramp voltage, typically 2v. allow the ramp peak to be as high as possible to maxi- mize the signal-to-noise ratio. the low-frequency small- signal gain of the power stage, gps (the gain from the inverting input of the pwm comparator to the output) can be calculated by using the following formula: where n sp is the secondary-to-primary power trans- former turns ratio. internal regulators the MAX5051 has two internal linear regulators that are used to power internal and external control circuits. the 9v regulator, reg9, is primarily used to power the high- and low-side gate drivers. bypass reg9 with a 4.7f ceramic capacitor or any other high-quality capacitor; use low-value ceramics in parallel as necessary. a 5v regulator also is provided, reg5, primarily used to bias the internal circuitry of the MAX5051. bypass reg5 with a 4.7f ceramic capacitor similar to the one used for reg9. both of these regulators are always powered. when using bootstrapped startup through a bleed resis- tor, do not load these outputs while the MAX5051 is in standby as it may fail to start. any external loading to this output should be such that the sum of their load and the standby current through pvin of the MAX5051 is less than the current that the bleed resistor can supply. startup modes the MAX5051 can be configured for two different startup modes, allowing operation in either boot- strapped or direct power mode. direct power mode in direct power mode, avin and pvin are connected directly to the input supply. this is typical in 12v to 24v systems. the undervoltage lockout set at stt needs to be adjusted down with an external resistor-divider to an appropriate level. bootstrapped startup in bootstrap mode, a resistor is connected from the input supply to pvin, where a capacitor to gnd is charged towards the input supply. when this voltage reaches the startup threshold, the device wakes up and begins switching. a tertiary winding from the trans- former is then used to sustain operation. the MAX5051 draws little current from pvin before reaching the threshold, which allows a large-value bootstrap resistor and reduces its power dissipation after startup. a large startup hysteresis helps the design of the bootstrap circuit by providing longer running times during startup. after coming out of standby and before initiating the soft-start, the MAX5051 turns on the low-side fet to charge up the boost capacitor. a voltage detector has been incorporated in the high-side driver that prevents the high-side switch from turning on with insufficient voltage. it is also used to indicate when the boost capacitor has been charged. once the capacitor is charged, soft-start commences. if the duty cycle is low, the magnetizing energy in the transformer may be insufficient to keep the bootstrap capacitor charged. drvb (see figure 2 dotted lines) has been provided to drive a small external fet connected between xfrmrh and pgnd, and is pulsed every cycle to keep the capacitor charged. gnr c f ps sp rcff rcff s = rc v fv rcff rcff inuvlo s rpp 2 cfst css ss = 56 / MAX5051 parallelable, clamped two-switch power-supply controller ic ______________________________________________________________________________________ 15
MAX5051 normally pvin is derived from a tertiary winding of the transformer. however, at startup there is no energy delivered through the transformer, hence, a special bootstrap sequence is required. figure 6 shows the voltages on pvin, reg9, and reg5 during startup. initially, pvin, reg9, and reg5 are 0v. after the input voltage is applied, c21 (figure 8) charges pvin through the startup resistor, r22, to an intermediate voltage. at this point, the internal regulators begin charging c3 and c4. the MAX5051 uses only 400a (typ) of the current supplied by r22, and the remaining current charges c21, c3, and c4. the charging of c4 and c3 stops when their voltages reach approximately 5v and 9v, respectively, while pvin continues rising until it reaches the wakeup level of 24v. once pvin exceeds this wakeup level, switching of the external mosfets begins and energy is transferred to the sec- ondary and tertiary outputs. when the voltage on the tertiary output builds to higher than 9v, startup has been accomplished and operation is sustained. however, if reg9 drops below 6.2v (typ) before startup is complete, the device goes back into standby. in this case, increase the value of c21 to store enough energy allowing for voltage buildup at the tertiary winding. startup time considerations the pvin bypass capacitor, c21, supplies current immediately after wakeup (see figure 8). the size of c21 and the connection of the tertiary winding deter- mine the number of cycles available for startup. large values of c21 increase the startup time and supply gate charge for more cycles during initial startup. if the value of c21 is too small, reg9 drops below 6.2v because the mosfets did not have enough time to switch and build up sufficient voltage across the tertiary output to power the device. the device goes back into standby and will not attempt to restart until pvin rises above 24v. use a low-leakage capacitor for c21, c3, and c4 (see figure 8). generally, power supplies keep typical startup times to less than 500ms even in low-line conditions (36vdc for telecom applications). size the startup resistor, r22 (figure 8) to supply both the maxi- mum startup bias of the device and the charging cur- rent for c21, c3, and c4. oscillator and synchronization the MAX5051 oscillator is externally programmable through a resistor and capacitor connected to rcosc. the pwm frequency will be 1/2 the frequency at rcosc with a 50% duty cycle, and is available at syncout. the maximum duty cycle is limited to < 50% by a 60ns internal blanking circuit in the power drivers in addition to the gate and driver delays. use the following formula to calculate the oscillator components: where c pcb is the stray capacitance on the pc board (about 14pf), reg5 = 5v, v th is the rcosc peak trip level, and f s is the switching frequency. the MAX5051 contains circuitry that allows it to be syn- chronized to an external clock whose duty cycle is 50%. for proper synchronization, the frequency of this clock should be 15% to 20% higher than half the rcosc fre- quency of the MAX5051 s internal oscillator. this is because the external source syncin directly drives the power stage, whereas the internal clock is divided by two. the synchronization feature in the MAX5051 has been designed primarily for two devices connected to the same power source with a short physical distance between the two circuits. under these circumstances, the syncout from one of the circuits can be connect- ed to the syncin of the other one; this forces the power cycle of the second unit to be 180 out-of-phase. to synchronize a second MAX5051, feed the syncout of the first device to the syncin of the second device. if necessary, many devices can be daisy-chained in this manner. each device will then have 180 phase differ- ence from the device that drives it. r rcosc s rcosc pcb th fc c in reg reg v () + ? ? ? ? ? ? ? 1 2 5 5 parallelable, clamped two-switch power-supply controller ic 16 ______________________________________________________________________________________ 40ms/div reg9 5v/div pvin 10v/div reg5 5v/div figure 6. pvin, reg5, and reg9 during startup in bootstrapped mode
integrating fault protection the integrating fault protection feature allows transient overcurrent conditions to be ignored for a programmable amount of time, giving the power supply time to behave like a current source to the load. this can happen, for example, under load-current transients when the control loop requests maximum current to keep the output voltage from going out of regulation. the fault integration time can be programmed externally by con- necting a suitably sized capacitor to the fltint pin. under sustained overcurrent faults, the voltage across this capacitor is allowed to ramp up towards the fltint shutdown threshold (2.9v, typ). once the threshold is reached, the power supply shuts down. a high-value bleed resistor connected in parallel with the fltint capacitor allows it to discharge towards the restart threshold (1.8v, typ). once this threshold is reached, the supply restarts with a new soft-started cycle. note that cycle-by-cycle current limiting is provided at all times by cs with a threshold of 154mv (typ). the fault integration circuit works by forcing a 90a current out of fltint every time that the current-limit compara- tor (figure 1, cilim) is tripped. use the following formu- la to calculate the value of the capacitor necessary for the desired shutdown time of this circuit. where i fltint = 90a, t sh is the desired fault integra- tion time after the first shutdown cycle during which current-limit events from the current-limit comparator are ignored. for example, a 0.1f capacitor gives a fault integration time of 2.25ms. some testing may be required to fine-tune the actual value of the capacitor. to calculate the required bleed resistance r fltint , use the following formula: where t rt is the desired recovery time. typically choose t rt = 10 x t sh . typical values for t sh range from a few hundred microseconds to a few mil- liseconds. synchronizing primary-side startup for parallel operation figure 7 shows the connection diagram of two or more MAX5051s for synchronized primary-side operation. the common connection of startup ensures all paral- leled modules wakeup and shutdown in tandem. this helps prevent startup conflicts when the secondaries of the power supplies are paralleled. connecting syncout to syncin is not necessary; however, when used, this minimizes the ripple current though the input bypass capacitors. applications information isolated telecom power supply figure 8 shows a complete design of an isolated syn- chronously rectified power supply with a 36v to 72v telecom voltage range. this power supply is fully pro- tected and can sustain a continuous short circuit at its output terminals. figures 9 though 14 show some of the performance aspects of this power-supply design. this circuit is available as a completely built and tested evaluation kit. r t c fltint rt fltint = 0 372 . c it v fltint fltint sh = . 09 MAX5051 parallelable, clamped two-switch power-supply controller ic ______________________________________________________________________________________ 17 rcosc con rcff syncin uvlo startup syncout fltint rcosc con rcff syncin uvlo startup syncout fltint #1 #2 MAX5051 MAX5051 figure 7. connection for synchronized startup of two or more MAX5051s
MAX5051 parallelable, clamped two-switch power-supply controller ic 18 ______________________________________________________________________________________ reg5 r21 24.9k ? 1% c1 100pf 1 rcosc +v in tp1 r25 100k ? c2 390pf 3 rcff 5 css 4 com 6 comp 7 fb 8 reg5 2 syncout c5 4700pf d8 21 r15 31.6k ? 1% r16 10.5k ? 1% c4 4.7 f reg5 reg5 9 reg9 c3 4.7 f reg9 10 pvin c6 0.1 f pvin 11 stt 12 lxvdd 13 lxh c18 100pf r27 10 ? c19 1 f lxh tp3 14 lxl r3 2.2k ? r11 360 ? c17 0.33 f c24 1000pf 4 3 1 2 u2 r20 0 ? r19 475 ? r12 100k ? 1% c27 0.15 f c36 0.22 f c28 0.047 f r1 11.5k ? 1% r2 2.55k ? 1% v out r23 10 ? trim sense (+) sense (-) r24 10 ? 3 52 1 4 out in pgnd gnd fb u3 reg9 c26 0.1 f c22 2200pf 2kv syncin 28 gnd 24 avin 23 bst 22 drvh 21 xfrmrh 20 uvlo 25 fltint 27 startup on/off 26 r4 1m ? 1% r6 1m ? 1% c7 0.22 f +v in +vin reg9 +v in r5 38.3k ? 1% d1 r7 0 ? r8 8.2 ? 2 c8 4.7 f xfrmrh drvb 19 drvdd 18 pgnd 17 drvl 16 cs 15 ic_paddle drvb reg9 c9 1 f r14 150 ? r9 8.2 ? c20 220pf d3 12 6 5 4 1 2 3 7 8 n2 r17 0.027 ? 1% c21 4.7 f 80v r18 4.7 ? pvin +v in r22 15k ? 1 2 1 6 d5 4t r13 47 ? c34 330pf 2 5 8t d7 1 2 3 2 1 4 5 6 6 7 8 n3 d4 1 2 3 2 1 4 5 7 8 n4 r10 20 ? c23 1000pf 8 10 2t t1 l1 2.4 h 5v 5v 5v c29 0.1 f 3 2 1 1 2 3 4 5 6 6 5 4 n_out p_out v+ gnd in- in+ u4 u5 v+ p_out m_out in+ in- gnd u7 c30 0.1 f 5v c31 0.1 f 5 4 3 1 2 vcc out gnd u1: MAX5051 u2: ps2913-1-m u3: max8515 u4, u7: max5048a u5: max5023m u6: ps9715 n1, n2: si4486 n3, n4: si4864 n5: bss123 an ca u6 lxh r26 560 ? r28 2k ? c13 270 f 4v c14 270 f 4v c15 270 f 4v c33 1 f 10v v out vout sgnd 5v +v in c16 3.3 f 21 d6 c35 1 f c32 1 f 1 2 3 4 8 7 6 5 in out wdi n.c. en gnd reset hold 21 d2 n1 3 2 1 8 7 6 5 4 xfrmrh xfrmrh c10 0.47 f 100v c11 0.47 f 100v c12 1 f 100v c25 0.07 f 100v -v in +v in n5 3 2 1 r29 1 ? xfrmrh drvb MAX5051 u1 reg5 v out v out figure 8. schematic of a 48v input 3.3v at 15a output synchronously rectified, isolated power supply
MAX5051 parallelable, clamped two-switch power-supply controller ic ______________________________________________________________________________________ 19 1 0 2 4 3 6 7 5 8 046 2 8 10 12 14 load current (a) power dissipation (w) figure 9. efficiency at nominal output voltage vs. load current 48v nominal input voltage 60 65 75 70 85 90 80 95 046 2 8 10 12 14 load current (a) efficiency (%) figure 10. power dissipation at nominal output voltage vs. load current for 48v input voltage. r l = 0.22 ? 4ms/div i out 5a/div v out 1v/div figure 11. turn-on transient at full load (resistive load) v out 100mv/div 50% > 75% > 50% of i out(max) , dl/dt = 5a/ s i out 5a/div 1ms/div figure 12. output voltage response to step-change in load current
MAX5051 parallelable, clamped two-switch power-supply controller ic 20 ______________________________________________________________________________________ v out 50mv/div 2 s/div figure 13. output voltage ripple at nominal input voltage and full load current (scope bandwidth = 20mhz) i out 10a/div i out 10a/div a: 1ms/div b: 20ms/div a b figure 14. load current (10a/div) as a function of time when the converter attempts to turn on into a 50m ? short circuit chip information transistor count: 2049 process: bicmos/dmos exposed paddle connected to gnd 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 syncin fltint startup uvlo gnd avin cs bst drvh xfrmrh drvb drvdd pgnd drvl lxl lxh lxvdd stt pvin reg9 reg5 fb comp css con rcff syncout rcosc tssop top view exposed paddle is internally connected to gnd. MAX5051 pin configuration
MAX5051 parallelable, clamped two-switch power-supply controller ic maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 21 ? 2003 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/packages .) tssop 4.4mm body.eps

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